Hello, the title of this video is, "How to Estimate Voltage Spikes from Layout Parasitic
Inductance in Switched-Mode Power Supplies".
My name is Colin Warwick, I'm the product manager for power electronics at Keysight
EEsof EDA.
The trend in switched-mode power supplies is to use wide band gap devices because these
enable a higher switching frequency and higher edge speeds (the "di/dt" of the switched loop).
These two in turn enable a smaller, lighter, cheaper power supply because the magnetics
and the capacitors can be smaller if you switch them more frequently.
And the higher edge speeds enable higher efficiency: There's less heat dissipated when you have
lower switching losses and the transistors make the transitions more quickly.
But these high slew rates come with a dark side.
In particular, the large spike voltage and noise generated by the layout parasitics,
particularly the inductance of the PCB layout traces.
This phenomenon is often called conducted electromagnetic interference, or conducted
EMI.
For example, in this circuit, I sweep the edge speed to increase di/dt, and monitor
the spike voltage from the anode of the diode to ground.
It has a non-optimum trace length of around 50 mm in this case.
The result is of course, as I make the edge faster, the spike voltage gets bigger, and
bigger, and bigger.
We showed you how to deal with this in our previous video entitled "How to design DC-to-DC
Converters", but a frequently asked question was "When should I start to worry about layout
parasitic inductance?
Is there a quick rule of thumb that says kind of 'Caution: Further investigation is needed?'"
The answer is "yes" and this follow up video is about how to make these estimates.
It was inspired in part by Prof Robert Erickson's lecture notes entitled, "EMI and Layout Fundamentals
for Switched-Mode Circuits".
I include a link to that presentation in the notes that go with the download that accompanies
this video.
So, let me show you the rule of thumb, then I'll show you how I derived it, so you can
know the breadth of its applicability and some exceptions.
The quantity to calculate is this:
You take mu naught, which is the permeability of free space, multiply the length of the
loop, the switched loop, and divide by the load resistance.
This gives you a quantity in units of time.
So, the thing you have to consider is, if the rise time of your circuit approaches this
quantity, then you have to worry about layout parasitic inductance, and do further analysis.
Now in SI units, the permeability of free space, mu naught, is actually defined to be
4 pi 1e-7 H/m exactly.
But the problem is, one meter and one Henry scale is not really intuitive.
A more intuitive way of looking at this mu naught number is in nanohenries, which is
more the kind of value you get in the circuit, and millimeters, which is typically the kind
of size of a circuit.
So, it turns out that this number is 1.26 nH/mm; but for our purposes, we are going
to approximate quite heavily in this video.
So, I'm just going to round it down to 1 nH/mm to make it very easy to remember and more
intuitive.
So, given this approach to units, we can plug in some numbers and see where we should become
concerned.
So, the vacuum permeability we said was 1 nH/mm roughly.
Loop length in mm, to be consistent with units, so, let's take an example around a rather
large loop: 50 mm.
The load resistance in ohms, let's say we've got a 5V USB charger delivering 2A into a
smart phone.
So, the phone presents a 2.5 ohm load to the switched-mode power supply.
So, given this rule of thumb, we need to be concerned if the edge speed in nanoseconds
approaches 1 * 50 / 2.5 = 20 ns.
We have to use these units consistently.
But, if our switched-mode power supply edge approaches this value, then we need to be
concerned about voltage spikes.
So we start our derivation with the inductor equation: V_spike = L_parasitic * di/dt.
The current goes from zero to I_on in the edge rise time, tau.
So, di/dt is simply I_on divided by tau.
So, the next step is to define a quantity R effective (R_eff) with units of ohms.
This isn't a real physical resistor, but it has units of resistance, so I give it a letter
R.
But it's just the ratio of the voltage across the switch when it's off, to the current through
the switch when it's on.
And a quick way to estimate R_eff if you don't know V_off or I_on is, in general for switched-mode
power concverters, R_eff is something on the order of R_load, and the coefficient between
R_load and R_eff is a function of the duty cycle, some simple artifact of the duty cycle.
For example, for a simple buck, the function is just 1/D, the duty cycle.
So, for example, when the D is a half for the buck circuit, R_eff is simply twice the
load resistance.
So, if you know the load resistance, just double that to get R_eff.
But usually you do know V_off and I_on, so this is just a more accurate way of doing
it, assuming you have those two numbers available.
So, the next step is to take our inductor equation and substitute for I-on and rearrange,
and we get this formula V_spike / V_off = L_parasitic / (tau * R_eff)
The next step is to observe that V_spike must be a lot less that V_off.
The ratio should be like 1% if its ripple is the limit, maybe 10% if device overstress
is the limit.
But in any case, V_spike must be a lot less that V_off.
And because V_spike over V-off is equal to L_parasitic over (tau*R_eff), that implies
that this quantity also must be less than one because these two quantities are equal.
So, if we rearrange this right-hand part here, we end up with the tau > L_parasitic / R_eff
for freedom form large spikes.
So, the next question is how big is L_parasitic?
Now let's say that you don't have a field solver handy and you want to know what the
inductance is.
You can use the algebraic formula from a book.
You'll see these seem to be quite complicated; but at their core, they're actually quite
simple.
All of these things summarize down into three parts.
One is the permeability of space.
The second is some kind of length, geometric length of the loop.
And the third is what we call a form factor, which is usually the logarithm of the ratio
of two geometric factors.
And because the geometric factors are almost always on the same order of magnitude, this
logarithmic form factor is on the order of one.
So we'll approximate that as one, and we're just reduced to the permeability of free space,
and the length of the loop.
I'm assuming of course here that the loop is one turn.
If you have more than one turn, obviously you've got an n-squared factor.
But here, in our case, the loop is one turn.
And so, it reduces down to this form factor on the order of unity, permeability of free
space, and a loop length, maybe a factor of 2 pi or whatever but, as an approximation,
we just take the loop length and multiply it by the permeability of free space.
So, our final rule of thumb is that the rise time must be greater than the permeability
of free space, which is about 1 nH per mm, times the loop length in mm, divided by the
R_eff, which is V_off over I_on, for freedom from large spikes.
If you don't have R_eff as mentioned in the beginning, use R_load instead, it's about
the same thing.
In that case, the rise time must be much greater than the permeability of free space, the loop
length divided by R_load.
So, how does this rule of thumb work out in practice?
I've coded up this equation in ADS here, and let's compare it to the accurate result from
the circuit solver.
You can see the spike here is around just under 3 volts, and the formula is about under
3 volts.
So let's sharpen up the edge and see how the spike grows as we did before, but now we're
also recalculating our rule of thumb.
And it has the right general trend.
It's not super accurate, but that's not surprising given the number of approximations we've got
in here.
But you can see when the edge gets sharper we're going from just under 3 volts to about
6 volts here.
So, it works pretty well, but obviously it's not as accurate as a field solver.
Now this parasitic inductance for a planar loop can be quite large.
Obviously, this can be on the order of millimeters.
This is nanohenries per millimeter, so this can be quite a large number.
It can be several nanohenries, and if it's on the order of a unit ohm, then the rise
time limit is going to be 10s of nano seconds.
What we'd really like to do is to get this inductance down.
Is there any way of getting this inductance down?
Indeed, if you break away from planar loops, there is.
What about non-planar loops?
If you take the loop to be on a multi-level non-planar loop, where one trace is the outbound
current and then some kind of ground plane to return the current, we can break this model
of the form factor, and end up with a new form factor which depends now on the thickness
of the insulator.
And this is important because we can make the thickness of this insulator quite small;
we can make this below a millimeter.
Typically a printed circuit board, the insulator is .1 mm or so.
So, this gives us a way of making this loop inductance a lot smaller.
We still have to count up the number of squares on the loop.
In other words, the loop length divded by the width of the trace.
But we can make this width quite broad, and we can make the insulator quite thin.
So this gives you a much lower inductance per unit length.
It can be .1 of a nanohenry per millimeter or less, for a given length of the loop.
So, this method is widely used.
You put in the ground plane effectively and you can reduce the inductance quite considerably.
In the download we have three layout examples, 2 planar loops, one's larger than the other,
the third example is this idea of using a ground plane to reduce the loop inductance
considerably.
So, now we've got our rule of thumb for a couple of cases, those planar loops, and the
non-planar loops.
Now we've got that number, why bother to use the EM field solver?
Of course, the rule of thumb is just an approximation; there's probably factors of 2 pi in there,
and so on.
It's not accurate enough to base a real design off of.
You want to use an EM field solver to get accuracy.
With the EM field solver, you get numerical solutions of Maxwell's Equations.
You take into account the exact geometry, and all the fringing effects that we neglected,
or factors of 2 pi, and log, a over b and so on.
The other thing to remember is that PCB traces are not pure inductors, they're not even purely
lumped elements, they're actually distributed elements.
An EM field solvers give the EM-based model based on network parameters.
Now you don't have to be familiar with network parameters, it all happens under the hood.
But the point is that, the EM field solvers will have the ability to model distributed
elements, not just simple L/C type of elements.
The other thing that field solvers can take into account is skin depth and surface roughness
of conductors.
They've become increasingly important with the high frequency harmonics of your square
wave.
And the other thing they can take into account is frequency-dependent dielectric constant,
shows the impact especially on the capacitive part.
As I mentioned, the traces are not purely inductors, they're more like R/L/C/G type
elements, but they're not even lumped elements, they're distributed R/L/C/G ladders if you
like.
So once you've violated this rule of thumb and the rise time gets close to that rule
of thumb, I recommend you use a field solver and get an accurate answer and explore the
design space.
You can play around with the loop geometries, compare planar versus non-planar loop, and
do an accurate model of your design.
So here's a summary and the next step, which is to get the example file.
We gave you the understanding of how to estimate when voltage spikes from layout parasitic
inductance start to become a problem in a switched-mode power supply.
The rules of thumb we developed for a planar loop is shown here, and a two-layer loop is
shown here.
We learned that two layer loops have a much lower inductance than a planar loop of about
the same size.
We learned that you have to use a field solver to create an accurate EM-based model if the
rule of thumb is violated when you start to approach this quantity.
You can download the example files that I showed today at this URL.
Or you can click on the link in the Description area.
And thank you for watching this video.
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